This board carries the MC68B54 ADLC Controller and Econet physical layer interfacing pretty much as per the A3020/A4000 Econet Module. I have used a 75159 line driver rather than the 26LS30 type used because they are more widely available (well I have more). RTS, which enables the line driver can be provided either directly from the 68B54 (as in most other Econet interfaces I have seen) or from monostable (IC3) selectable by LK1, normally the monostable should be selected.
The 68B54 Interrupt, which drives NMI, can be enabled/disabled by the CPU writing to one of two I/O addresses ($FC24/$FC28) which in turn controls an Econet Interrupt Enable signal, this is ANDed with the interrupt signal by IC8.
I have used the signal which would normally be used to enable the built-in Econet clock generator to signal that a valid Econet clock has been detected via a front panel mounted LED connected to SK1. This 'Econet Clock Status' signal comes from the FDC Latch ( aka the 'Miscellaneous Function Latch') which is on the FDC board, the signal is routed to this board as it seems more sensible for the LED to be on the Econet front panel.
ADLC (IC1) MC68B54 Registers
| Register Address | Register Name | Function |
| $FC20 | ADLC0 | Control Register 1 /Status Register 1 |
| $FC21 | ADLC1 | Control Register 2&3 / Status Register 2 |
| $FC22 | ADLC2 | Transmit FIFO (Frame Continue) / Receive FIFO |
| $FC23 | ADLC3 | Transmit FIFO (Frame Terminate) / Receive FIFO |
Schematic
Bill Of Materials
Front Panel
PCB
